The present invention relates to a class-D power amplifier and, more particularly, to a class-D power amplifier that enables reduction of beat noise and that is suitable for amplifying power of an audio signal.
A hitherto known self-excitation class-D amplifier includes an integrating circuit, a comparator which receives an output from the integrating circuit as an input; a switching circuit which is activated by an output from the comparator; and a low-pass filter connected to an output side of the switching circuit. A feedback is applied from an output terminal of the low-pass filter to the comparator by way of a first feedback circuit. Another feedback is applied from the output terminal of the low-pass filter to an input terminal of the integrating circuit by way of a second feedback circuit (see JP-B-61-21007).
A class-D power amplifier using a switching power source is described in JP-A-2006-60580. When power is fed to a class-D amplifying circuit by the switching power source, a difference between a switching frequency f1 of the class-D amplifying circuit and a switching frequency f2 of the switching power source; namely, Δf=abs(f1−f2), causes beat noise, which in turn deteriorates sound quality. In light of this, the switching frequency of the class-D amplifying circuit and the switching frequency of the switching power source are synchronized to each other, thereby reducing the beat noise.
A pulse modulator 120 of a class-D amplifier (a digital amplifying module 100) described in JP-A-2006-60580 includes a logic circuit (a D flip flop 174) that is provided in a PWM loop circuit and that is synchronized with a clock signal (FIG. 3 of JP-A-2006-60580). In the configuration, since the D flip flop 174 is inserted into an arbitrary point in the loop circuit, the class-D amplifier cannot perform operation out of synchronization with an input synchronization clock signal.
In the hitherto self-excitation class-D amplifier described in JP-B-61-21007, when an output level of the amplifier becomes greater, a frequency of self excitation generally decreases, whereby a total harmonic distortion (THD) of the output is reduced. Meanwhile, according to the technique described in JP-A-2006-60580, the amplifier cannot perform operation out of synchronization with an external clock signal. Hence, when a large output is produced, an amount of negative feedback from the output terminal to the input terminal is decreased, and THD becomes worse.
Moreover, there is a necessity for feeding a stable clock signal to the D flip flop 174 described in JP-A-2006-60580. For this reason, a PLL circuit 176 is adopted as a synchronization clock signal generator. However, the PLL circuit has a complicate configuration and suffers an inconvenience of an increase in an entire scale of circuitry.